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[VHDL-FPGA-Verilog] DDR

Description: leon ep2s60 ddr use altera statix2 and add ddr sdram-leon ep2s60 ddr
Platform: | Size: 752640 | Author: free | Hits:

[VHDL-FPGA-Verilog] DE2_70_NIOS_14_ssram

Description: Altera公司DE-70开发板中16位SDRAM的32位用法，纯硬件实现哦-Altera DE-70 16MX16SDRAM =>32bits
Platform: | Size: 1120256 | Author: qw | Hits:

[ARM-PowerPC-ColdFire-MIPS] tst_lcd

Description: 测试字符型LCD 和 SDRAM的代码 在altera IDE 7.2 下测试通过-Test character LCD and SDRAM' s code under test altera IDE 7.2
Platform: | Size: 450560 | Author: liuzhenyu | Hits:

[VHDL-FPGA-Verilog] fpga-display-bmp-pictures

Description: 本文设计的是基于大规模FPGA的BMP图库管理，完成了数码相框的一部分功能。并且本文详细地介绍了BMP图库管理的软硬件实现，即采用Altera的CyclonII系列EP2C20F484C7作为主控芯片，内嵌32位的NiosII软核，采用SDRAM作为内存，把存储在SD卡内的二进制图片信息读入内存，并控制TFT彩色液晶，读取图片数据送到液晶上显示。整个过程的所有设备都是通过Avalon总线挂在NiosII上，在NiosII的协调下正常工作。 本作品最终能显示存入SD卡内的彩色图片信息，图片显示很流畅，没有延时。并且能通过4个按键分别完成图片的上翻、下翻、放大和缩小。-This design is based on the large-scale FPGA-BMP library management, and completed part of the features of digital photo frame. This paper describes the library management software and hardware to achieve BMP photos, that used the Altera s CyclonII series EP2C20F484C7 as the master chip, embedded soft-core 32-bit NiosII, the use of SDRAM for memory, SD card stored the binary picture information read into memory, and control TFT color LCD, read the image form the memory data to the LCD display. All equipment of the process hanging in the NiosII through Avalon bus, with the NiosII CPU and complete the coordination of work. Eventually the work can show the color pictures of information stored into the SD card, pictures show smoothly, and with no delay. And with 4 keys, respectively, we can make the TFT display the previous image or the next image,and make the pictures zoom in or zoom out.
Platform: | Size: 2168832 | Author: wuwei | Hits:

[VHDL-FPGA-Verilog] DE1_fat32

Description: 本文设计的是基于大规模FPGA的BMP图库管理，完成了数码相框的一部分功能。并且本文详细地介绍了BMP图库管理的软硬件实现，即采用Altera的CyclonII系列EP2C20F484C7作为主控芯片，内嵌32位的NiosII软核，采用SDRAM作为内存，把存储在SD卡内的二进制图片信息读入内存，并控制TFT彩色液晶，读取图片数据送到液晶上显示。整个过程的所有设备都是通过Avalon总线挂在NiosII上，在NiosII的协调下正常工作。 本作品最终能显示存入SD卡内的彩色图片信息，图片显示很流畅，没有延时。并且能通过4个按键分别完成图片的上翻、下翻、放大和缩小。-This design is based on the large-scale FPGA-BMP library management, and completed part of the features of digital photo frame. This paper describes the library management software and hardware to achieve BMP photos, that used the Altera s CyclonII series EP2C20F484C7 as the master chip, embedded soft-core 32-bit NiosII, the use of SDRAM for memory, SD card stored the binary picture information read into memory, and control TFT color LCD, read the image form the memory data to the LCD display. All equipment of the process hanging in the NiosII through Avalon bus, with the NiosII CPU and complete the coordination of work. Eventually the work can show the color pictures of information stored into the SD card, pictures show smoothly, and with no delay. And with 4 keys, respectively, we can make the TFT display the previous image or the next image,and make the pictures zoom in or zoom out.
Platform: | Size: 11721728 | Author: wuwei | Hits:

[VHDL-FPGA-Verilog] source

Description: SDRAM控制器源代码，是ALTERA公司的IP源核，很好很强大-SDRAM controller source code, very very strong
Platform: | Size: 11264 | Author: 张理 | Hits:

[Software Engineering] sdr_sdram_altera

Description: ALTERA的SDRAM的控制器和时序文档说明，很详细也很简洁，是一份不可多得的SDRAM开发的参考文档-ALTERA and timing of the SDRAM controller documentation, very detailed but also very simple, is a rare development of reference documentation SDRAM
Platform: | Size: 701440 | Author: 张理 | Hits:

[Windows Develop] treff-ddr-sdrh

Description: 本程序源码是DDR SDRAM控制器的VHDL程序源源码，由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
Platform: | Size: 439296 | Author: wyq52103 | Hits:

[source in ebook] 1_sdram_controller

Description: 这是altera公司的sdram IP core的用户使用指南，可以参考这个自己开发-sdram control ip core
Platform: | Size: 195584 | Author: 瑾琨 | Hits:

[Embeded-SCM Develop] memorynios

Description: Altera Fpga 的存储器应用。主要以SDRAM、FLASH、SRAM存储器为主的FPGA存储器系统的扩充与应用。-Altera Fpga memory applications. Main the FPGA memory system based SDRAM, FLASH, SRAM memory expansion.
Platform: | Size: 679936 | Author: TangTang | Hits:

[VHDL-FPGA-Verilog] dab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[VHDL-FPGA-Verilog] my_test_rw_pack9

Description: 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclone EP1C12Q240C8N SDRAM: HY57V283220T-6
Platform: | Size: 3520512 | Author: TYS | Hits:

[ARM-PowerPC-ColdFire-MIPS] FA161-SCH

Description: 联华众科FPGA开发板FA161核心器件为 Altera Cyclone系列FPGA EP1C6，FA161板载有SDRAM，SRAM，FLASH方便制作各种应用，开发板所带资料中包括了上位机与开发板USB通信，上位机与开发板以太网通信，上位机与开发板串口通信例程。FA161板载有USB 1.1，USB 2.0(CY7C68013A)接口，以太网接口(RTL8019AS)。FA161上可以进行HDL程序开发，可以进行nios ii程序开发，可以结合MATLAB制作DSP Builder应用。FA161上可以运行uClinux和Micro C/OS-II实时操作系统。-Lianhua Branch FPGA development board FA161 core device for Altera Cyclone series FPGA EP1C6 FA161 onboard SDRAM, SRAM, FLASH facilitate the production of a variety of applications, including the host computer and the development board development board brought information USB communication, the PCdevelopment board Ethernet communication, the host computer and the development board serial communication routines. The FA161-board have USB 1.1, USB 2.0 (CY7C68013A) interface, Ethernet interface (RTL8019AS). HDL program development, FA161 can be nios ii program development, combination of MATLAB production DSP Builder application. The FA161 can run uClinux and Micro C/OS-II real-time operating system.
Platform: | Size: 2085888 | Author: qchwu | Hits:

[VHDL-FPGA-Verilog] vga_memory

Description: 基于ALTERA DE2 开发板开发的关于SDRAM，SRAM以及FlashMemory的程序-ALTERA DE2 development board based on the development of SDRAM, SRAM and procedures FlashMemory
Platform: | Size: 3448832 | Author: 善解人衣 | Hits:

[VHDL-FPGA-Verilog] Using_the_SDRAM_on_DE0_Board

Description: Using the SDRAM on Altera’s DE0 Board with VHDL Designs
Platform: | Size: 1879040 | Author: sanya | Hits:

[Other] sdram_controller

Description: sdram control base of altera avolon bus
Platform: | Size: 4096 | Author: wang | Hits:

[VHDL-FPGA-Verilog] 61EDA_C915

Description: altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
Platform: | Size: 2325504 | Author: 杜小方 | Hits:

[VHDL-FPGA-Verilog] test_sdram

Description: 原创的altera de2-70 FPGA板功能测试实验，用于SDram的读写。包含完整源代码，仿真文件，可直接下载到板子上的SOF文件，适合初学者研习。-Original altera de2-70 FPGA board function test, used for SDram read and write. Contains the complete source code, the simulation files, can be directly downloaded to the board on the SOF file, suitable for beginners to study.
Platform: | Size: 3628032 | Author: YUKAI ZHANG | Hits:

[VHDL-FPGA-Verilog] test_spi

Description: 原创的altera de2-70 FPGA板功能测试实验，用于spi的读写。包含完整源代码，仿真文件，可直接下载到板子上的SOF文件，适合初学者研习。-Original altera de2-70 FPGA board function test, used for SDram read and write. Contains the complete source code, the simulation files, can be directly downloaded to the board on the SOF file, suitable for beginners to study.
Platform: | Size: 374784 | Author: YUKAI ZHANG | Hits:

[VHDL-FPGA-Verilog] SDRAM_CONTROL_DE2

Description: 基于Altera公司的Cyclone II 2C35芯片和SDRAM芯片IS42S16400的sdram控制器（教学用）-Based on Altera Cyclone II 2C35 chips and SDRAM chips IS42S16400. the code realize a the sdram controller (for teaching)
Platform: | Size: 5433344 | Author: 徐昊 | Hits:
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